The Design & Verification Conference & Exhibition is the premier conference for functional design and verification, focused on bringing information from the leading edge of technology, techniques, standards and methods.
DVCon - February 25-28, 2013
Thank you attendees and exhibitors for making this a record breaking year. See you next year at DVCon 2013.
DVCon 2012 Papers and Speakers Slides will be available April 20th.
Did you miss the "The Resurgence of Chip Design" panel? Listen to it here!
Keynote Speaker:Aart de Geus
Chairman of the Board and Chief Executive Officer Synopsys, Inc.
Systemic Collaboration: Principles for Success in IC Design
John Aynsley, CTO - Doulos
A member of the IEEE 1666 SystemC (TM) Language Standard Working Group, is the first recipient of the Accellera Systems Initiative Technical Excellence Award. The Award recognizes the outstanding achievements John has made to the organization's SystemC standardization efforts.